Sawen Moerjie

Sawen_Blog

一个普通的传媒工科牲的博客
follow
HomeArchives数字通信FPGA

2023 National Competition C Problem "Capacitance and Inductance Measurement Device" Design Report

#电路#FPGA157
AI Translation
This post is translated from Chinese into English through AI.View Original
AI-generated summary
The document discusses the measurement principles of an LCR tester, which applies a sinusoidal excitation signal to a Device Under Test (DUT) and measures the voltage and current to determine the DUT's characteristics. It explains the behavior of an ideal capacitor and how real capacitors can be modeled with equivalent resistance and capacitance due to losses, leading to a phase difference in current and voltage. Key parameters such as capacitive reactance, resistance, quality factor (Q), and dissipation factor (D) are defined and calculated using orthogonal algorithms. The document also covers the simulation of parameters using an ADC and DAC, detailing the design of an LC filter to eliminate high-frequency noise. It describes the PCB design for measuring components, addressing impedance matching issues, and improvements made to enhance signal integrity. The FPGA programming section outlines the setup for acquiring current and voltage signals, generating excitation signals, and processing the data for phase shifting and filtering. Finally, it presents measurement results, including the outputs from low-pass filters and calculations for capacitive reactance, and discusses future plans for integrating SPI communication to transmit data for further processing.

Measurement Principles#

Refer to the solution on the website below

bookmark

Referring to the LCR tester, the basic working principle is to apply a sine excitation signal to the DUT, and then measure the voltage across the DUT and the current flowing through the DUT, from which the properties and parameters of the DUT can be calculated.

1720858696834.png

For an ideal capacitor, the current phase should lead the voltage across the capacitor by 90°. However, real capacitors have losses, which can be equivalent to a parallel combination of an ideal capacitor $C_p$ and an ideal resistor $R_p$. Therefore, the phase of the current leading the voltage will be less than 90°, and this phase difference is the loss angle.

2024after4202407131621163.png

Assuming the voltage across the DUT is $\dot{V}=V\cos(\omega t)$, the current flowing through the DUT is $\dot{I}=I \sin(\omega t - \varphi)$, the projection of the current on the imaginary axis is the current flowing through the ideal capacitor, and the projection on the real axis is the current flowing through the loss resistor.

Thus, the capacitive reactance of the parallel capacitor can be calculated as $X_{Cp}=\frac{V}{I \cos\varphi}$, and the capacitance value $C_P=\frac{1}{\omega X_{Cp}}=\frac{I \cos \varphi}{\omega V}$.

The value of the loss resistor is $R_p=\frac{V}{I \sin\varphi}$.

The ratio of the reactive power consumed by the component to the active power is defined as the Q value of the component, and the reciprocal of the Q value is the D value (tangent of the loss angle)

Q=RPXCp=cotφ,D=1Q=tanφQ=\frac{R_P}{X_{Cp}}=cot \varphi, D=\frac{1}{Q}=tan \varphi

The parameters needed above can be obtained using the orthogonal algorithm:

Isin⁡(ωt−φ)⋅Vcos⁡(ωt)=12VIsin⁡(2ωt−φ)−12VIsin⁡φIsin⁡(ωt−φ)⋅Vsin⁡(ωt)=−12VIcos⁡(2ωt−φ)+12VIcos⁡φ \begin{align}I\sin(\omega t-\varphi)\cdot V\cos(\omega t) & = \frac12VI\sin(2\omega t-\varphi)-\frac12VI\sin\varphi\\I\sin(\omega t-\varphi)\cdot V\sin(\omega t) & = -\frac12VI\cos(2\omega t-\varphi)+\frac12VI\cos\varphi \end{align}

After multiplying and passing through a low-pass filter, the DC components $-\frac{1}{2} VI \sin\varphi$ and $\frac{1}{2} VI \cos\varphi$ can be obtained, allowing the calculation of the required tangent of the loss angle

tanφ=VIsin⁡φVIcos⁡φtan\varphi = \frac{VI \sin \varphi}{VI \cos \varphi}

The following parameters can also be obtained

The capacitive reactance of the ideal capacitor in parallel Xcp=VIcos⁡φ=V2VIcos⁡φ, capacitance is Cp=1ωXcp, the loss resistor in parallel Rp=VIsin⁡φ=V2VIsin⁡φ. Where V2 can be obtained by squaring the voltage and filtering out high-frequency components.\text{The capacitive reactance of the ideal capacitor in parallel }X_{cp}=\frac V{I\cos\varphi}=\frac{V^2}{VI\cos\varphi} \text{, capacitance is }C_p=\frac1{\omega X_{cp}},\text{ the loss resistor in parallel }\\R_{p}=\frac V{I\sin\varphi}=\frac{V^2}{VI\sin\varphi}\text{. Where }V^2\text{ can be obtained by squaring the voltage and filtering out high-frequency components.}

Parameter Simulation#

The existing ADC input voltage range is 0~2V, with an input bias of 1V; the DAC output voltage range is 1V peak-to-peak, and it can also add bias,

1721052590800.png

The capacitance value is 1nF-100nF, and when the shunt resistor is 0.33Ω, the output voltage peak-to-peak value is 4-200mv. When measuring inductance at a frequency of 1MHz, with inductance values of 10uF-100uF, the output voltage peak-to-peak value is 15-150mv. Since the ADC module's input range is 0~2V, the signal is amplified by 9 times, with the peak-to-peak value amplified to about 1.8V.

Debugging Records#

The signal output from the DAC does not match the impedance of the LC filter, resulting in a low amplitude of the signal at the input of the LC filter.

After powering on the detection circuit for the DUT, there is a -500mv bias at the input.

The LC filter is designed as follows; when the DAC outputs a 1MHz signal, higher harmonics are quite severe, so an LC low-pass filter with a passband of 1.2MHz is designed to filter out high-frequency noise.

1721448168186.png

1721448231710.png

PCB Design#

Initial Version#

R8 is used to connect to the test fixture, the excitation signal enters from P1, passes through the capacitor or inductor under test on R8, and the current flows into the subsequent current detection circuit through C5,

2024after4202407211655761.svg

1721560509597.png

With this design, the input impedance of the circuit is the impedance value of the DUT at a specific frequency, while the output impedance of the front-end amplifier is 50Ω, which will cause the amplitude of the input signal to not be the expected value.

Improvement#

Remove the 50Ω resistor used for impedance matching at the output of the front-end amplifier, utilizing the characteristic of the operational amplifier that has a very low output impedance, ensuring that all the output signal voltage is applied to the input of the above circuit.

The reason for this improvement is that the operational amplifier's subsequent stage does not carry capacitive loads, and with the LC filter and long coaxial cable, the output does not need to connect to a matching resistor.

FPGA Program Design#

Based on the principles above, two ADCs are needed to collect current and voltage signals, and one DAC to generate the excitation signal. Therefore, the DE0nano is chosen, which has two extended 40-pin headers that can connect to two ADDA modules.

2024after4202407231614021.bmp

The FPGA's crystal oscillator frequency is 50MHz, and through PLL division, 20MHz and 80MHz are generated, where the ADC clock is 20M and the DAC clock is 80M. They are then connected to ADC_Interface and DAC_Interface respectively.

The signal width collected by the ADC is 10 bits, discarding the lowest two bits for subsequent signal processing. After collecting 1024 samples, it pauses for 0.5 seconds before the next collection.

The DAC section uses an NCO to generate a sine wave signal, switching the frequency word through a dip switch, outputting to DAC_interface, left-shifting by 1 bit before outputting, and then amplifying by 2 times through a non-inverting amplifier to enhance the signal's driving capability.

The current and voltage data collected by the ADC are stored in RAM, and phase shifting is achieved by changing the starting address for reading. The ADC's sampling rate is 20M, collecting 100K signals, with each cycle collecting 200 points. Therefore, to achieve a phase shift of π2\frac{\pi}{2}, it is only necessary to start reading data from 50 in RAM, and the read signal will be the signal read from RAM starting from 0, phase-shifted by π2\frac{\pi}{2}.

The data collected by the ADC is unsigned, and performing multiplication filtering will not match the calculation results. Therefore, an additional module is added to convert unsigned to signed numbers, and after conversion to signed numbers, multiplication is performed, followed by passing through a low-pass filter to obtain the required values. The output of the low-pass filter is truncated to retain only the high 16 bits of data, reducing the impact of jitter on the DC signal results.

Measurement Results#

1721657082949.png

The output of the first Lowpass is VIcos⁡ϕVI\cos\phi, the output of the second Lowpass is 12VIcos⁡φ\frac{1}{2}VI\cos \varphi, and the output of the third Lowpass is V2V^2. The calculation process for capacitive reactance is as follows:

Based on the fitting relationship between the simulated input current and output voltage, it can be obtained that the amplitude of the collected output voltage equals current ÷ 0.305, thus the capacitive reactance is the third output ÷ 2 ÷ the first output ÷ 0.305.

Circuit Display#

2024after4202407231606426.jpg

Future Plans#

Add SPI communication to transmit the sampled and calculated data to the TI development board for further computation and display.

Loading...
Ownership of this post data is guaranteed by blockchain and smart contracts to the creator alone.